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LTC1860L/LTC1861L Power, 3V, 12-Bit, 150ksps 1- and 2-Channel ADCs in MSOP
FEATURES
s s s s
DESCRIPTIO
s s
s s s s
12-Bit 150ksps ADCs in MSOP Package Single 3V Supply Low Supply Current: 450A (Typ) Auto Shutdown Reduces Supply Current to 10A at 1ksps True Differential Inputs 1-Channel (LTC1860L) or 2-Channel (LTC1861L) Versions SPI/MICROWIRETM Compatible Serial I/O High Speed Upgrade to LTC1285/LTC1288 Pin Compatible with 16-Bit LTC1864L/LTC1865L No Minimum Data Transfer Rate
The LTC(R)1860L/LTC1861L are 12-bit A/D converters that are offered in MSOP and SO-8 packages and operate on a single 3V supply. At 150ksps, the supply current is only 450A. The supply current drops at lower speeds because the LTC1860L/LTC1861L automatically power down between conversions. These 12-bit switched capacitor successive approximation ADCs include sample-and-holds. The LTC1860L has a differential analog input with an external reference pin. The LTC1861L offers a softwareselectable 2-channel MUX and an external reference pin on the MSOP version. The 3-wire, serial I/O, MSOP or SO-8 package and extremely high sample rate-to-power ratio make these ADCs ideal choices for compact, low power, high speed systems. These ADCs can be used in ratiometric applications or with external references. The high impedance analog inputs and the ability to operate with reduced spans down to 1V full scale allow direct connection to signal sources in many applications, eliminating the need for external gain stages.
, LTC and LT are registered trademarks of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corporation.
APPLICATIO S
s s s s
High Speed Data Acquisition Portable or Compact Instrumentation Low Power Battery-Operated Instrumentation Isolated and/or Remote Data Acquisition
TYPICAL APPLICATIO
1F
Supply Current vs Sampling Frequency Single 3V Supply, 150ksps, 12-Bit Sampling ADC
1000 CONV LOW = 1.5s TA = 25C VCC = 2.7V
LTC1860L 1 2 ANALOG INPUT 0V TO 3V 3 4 VREF IN + IN - GND VCC SCK SDO CONV 8 7 6 5
1860L TA01
SUPPLY CURRENT (A)
3V
100
10
SERIAL DATA LINK TO ASIC, PLD, MPU, DSP OR SHIFT REGISTERS
1
0.1 0.01
1 10 0.1 100 SAMPLING FREQUENCY (kHz)
U
1000
1860L/61L TA02
U
U
18601Lf
1
LTC1860L/LTC1861L
ABSOLUTE
AXI U
RATI GS
Supply Voltage (VCC) ................................................. 7V Ground Voltage Difference AGND, DGND LTC1861L MSOP Package ......... 0.3V Analog Input .................... (GND - 0.3V) to (VCC + 0.3V) Digital Input ..................................... (GND - 0.3V) to 7V Digital Output .................. (GND - 0.3V) to (VCC + 0.3V)
PACKAGE/ORDER I FOR ATIO
TOP VIEW VREF IN + IN GND 1 2 3 4 8 7 6 5 VCC SCK SDO CONV
ORDER PART NUMBER LTC1860LCMS8 LTC1860LIMS8 MS8 PART MARKING LTD2 LTD3 ORDER PART NUMBER LTC1860LCS8 LTC1860LIS8 S8 PART MARKING 1860L 1860LI
CONV CH0 CH1 AGND DGND 1 2 3 4 5
MS8 PACKAGE 8-LEAD PLASTIC MSOP
TJMAX = 150C, JA = 210C/W
TOP VIEW VREF 1 IN IN
+ -
8 VCC 7 SCK 6 SDO 5 CONV
2 3
GND 4
S8 PACKAGE 8-LEAD PLASTIC SO
TJMAX = 150C, JA = 175C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
CO VERTER A D
PARAMETER Resolution No Missing Codes Resolution INL Transition Noise Gain Error Offset Error Input Differential Voltage Range Absolute Input Range VREF Input Range Analog Input Leakage Current CIN Input Capacitance
ULTIPLEXER CHARACTERISTICS
CONDITIONS
q q
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. VCC = 2.7V, VREF = 2.5V, fSCK = fSCK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted.
MIN 12 12 1 0.13
q q
(Note 3)
VIN
= IN +
- IN -
IN+ Input IN- Input LTC1860L S0-8 and MSOP, LTC1861L MSOP (Note 4) In Sample Mode During Conversion
q
2
U
U
W
WW U
WU
W
(Notes 1, 2)
Power Dissipation .............................................. 400mW Operating Temperature Range LTC1860LC/LTC1861LC ......................... 0C to 70C LTC1860LI/LTC1861LI ...................... - 40C to 85C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C
TOP VIEW 10 9 8 7 6 VREF VCC SCK SDO SDI
ORDER PART NUMBER LTC1861LCMS LTC1861LIMS MS PART MARKING LTD4 LTD5 ORDER PART NUMBER LTC1861LCS8 LTC1861LIS8 S8 PART MARKING 1861L 1861LI
MS PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 150C, JA = 210C/W
TOP VIEW CONV 1 CH0 2 CH1 3 GND 4 8 VCC 7 SCK 6 SDO 5 SDI
S8 PACKAGE 8-LEAD PLASTIC SO
TJMAX = 150C, JA = 175C/W
U
TYP
MAX
UNITS Bits Bits LSB LSBRMS mV mV V V V V A pF pF
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q
20 2 0 - 0.05 - 0.05 1 12 5 5 VREF VCC + 0.05 VCC /2 VCC 1
q
LTC1860L/LTC1861L
DY A IC ACCURACY
TA = 25C. VCC = 3V, VREF = 3V, fSAMPLE = 150kHz, unless otherwise specified.
SYMBOL PARAMETER SNR THD Signal-to-Noise Ratio 1kHz Input Signal Total Hamonic Distortion Up to 5th Harmonic 1kHz Input Signal Full Power Bandwidth Full Linear Bandwidth S/(N + D) 68dB S/(N + D) Signal-to-Noise Plus Distortion Ratio CONDITIONS MIN TYP 72 72 86 10 30 MAX UNITS dB dB dB MHz kHz
DIGITAL A D DC ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER VIH VIL IIH IIL VOH VOL IOZ ISOURCE ISINK IREF ICC PD High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High Level Output Voltage Low Level Output Voltage Hi-Z Output Leakage Output Source Current Output Sink Current Reference Current (LTC1860L SO-8, MSOP and LTC1861L MSOP) Supply Current Power Dissipation CONDITIONS VCC = 3.3V VCC = 2.7V VIN = VCC VIN = 0V VCC = 2.7V, IO = 10A VCC = 2.7V, IO = 360A VCC = 2.7V, IO = 400A CONV = VCC VOUT = 0V VOUT = VCC CONV = VCC fSMPL = fSMPL(MAX) CONV = VCC After Conversion fSMPL = fSMPL(MAX) fSMPL = fSMPL(MAX)
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. VCC = 2.7V, VREF = 2.5V, unless otherwise noted.
MIN
q q q q q q q q
RECO
VCC fSCK tCYC tSMPL tsuCONV thDI tsuDI tWHCLK tWLCLK tWHCONV tWLCONV thCONV
full operating temperature range, otherwise specifications are TA = 25C.
SYMBOL PARAMETER Supply Voltage Clock Frequency Total Cycle Time Analog Input Sampling Time (Note 5) Setup Time CONV Before First SCK, (See Figure 1) Holdtime SDI After SCK Setup Time SDI Stable Before SCK SCK High Time SCK Low Time CONV High Time Between Data Transfer Cycles CONV Low Time During Data Transfer Hold Time CONV Low After Last SCK LTC1861L LTC1861L fSCK = fSCK(MAX) fSCK = fSCK(MAX) LTC1860L LTC1861L CONDITIONS
E DED OPERATI G CO DITIO S
U
U
U
U WW
U
WU
TYP
MAX 0.45 2.5 - 2.5
UNITS V V A A V V
1.9
2.3 2.1
2.6 2.45 0.3 3 - 6.5 6.5
V A mA mA
q q q q
0.001 0.01 0.5 0.45 1.22
3 0.1 10 1.0
A mA A mA mW
The q denotes specifications which apply over the
MIN 2.7
q
TYP
MAX 3.6 8
UNITS V MHz s SCK SCK ns ns ns 1/fSCK 1/fSCK s SCK ns
DC 12 * SCK + tCONV 12 10 60 30 30 45% 45% tCONV 12 26
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3
LTC1860L/LTC1861L
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. VCC = 2.7V, VREF = 2.5V, fSCK = fSCK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted.
SYMBOL tCONV tdDO tdis ten thDO tr tf PARAMETER Conversion Time (See Figure 1) Delay Time, SCK to SDO Data Valid Delay Time, CONV to SDO Hi-Z Delay Time, CONV to SDO Enabled Time Output Data Remains Valid After SCK SDO Rise Time SDO Fall Time CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF
q q q q
TI I G CHARACTERISTICS
fSMPL(MAX) Maximum Sampling Frequency
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to GND. Note 3: Integral nonlinearity is defined as deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band.
TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Sampling Frequency
1000 CONV LOW = 1.5s TA = 25C VCC = 2.7V 600 500 fS = 150kHz VCC = 2.7V VREF = 2.5V
SUPPLY CURRENT (A)
SUPPLY CURRENT (A)
100
SHUTDOWN CURRENT (A)
10
1
0.1 0.01
1 10 0.1 100 SAMPLING FREQUENCY (kHz)
4
UW
UW
CONDITIONS
q q
MIN 150
TYP 3.7 45 55 35
MAX 4.66 55 60 120 120
UNITS s kHz ns ns ns ns ns ns ns
5
15 25 12
Note 4: Channel leakage current is measured while the part is in sample mode. Note 5: Assumes fSCK = fSCK(MAX). In the case of the LTC1860L SCK does not have to be clocked during this time if the SDO data word is not desired. In the case of the LTC1861L a minimum of 2 clocks are required on the SCK input after CONV falls to configure the MUX during this time.
Supply Current vs Temperature
20
Sleep Current vs Temperature
fS = 150kHz VCC = 2.7V VREF = 2.5V
15
400 300 200 100 0 -50 -25
10
5
1000
50 25 75 0 TEMPERATURE (C)
100
125
0 -50 -25
50 25 75 0 TEMPERATURE (C)
100
125
1860L/61L G01
1860L/61L G02
1860L/61L G03
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LTC1860L/LTC1861L TYPICAL PERFOR A CE CHARACTERISTICS
Reference Current vs Sampling Rate
10 9
REFERENCE CURRENT (A)
REFERENCE CURRENT (A)
7 6 5 4 3 2 1 0 0 25 75 100 125 50 SAMPLING FREQUENCY (kHz) 150
REFERENCE CURRENT (A)
8
CONV LOW = 1.5s TA = 25C VCC = 2.7V VREF = 2.5V
Typical INL Curve
1.0 fS = 150kHz TA = 25C VCC = 2.7V VREF = 2.5V
DNL ERROR (LSBs)
ANALOG INPUT LEAKAGE (nA)
0.5
INL ERROR (LSBs)
0
-0.5
-1.0
0
512 1024 1536 2048 2560 3072 3584 4096 CODE
1860L/61L G07
Change in Offset vs Reference Voltage
2 fS = 150kHz TA = 25C VCC = 3.6V
CHANGE IN OFFSET (LSB)
1
CHANGE IN OFFSET (LSB)
0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8
GHANGE IN GAIN ERROR (LSB)
0
-1
-2
0
2 3 1 REFERENCE VOLTAGE (V)
UW
1860L/61L G04 1860L/61L G10
Reference Current vs Temperature
25 fS = 150kHz VCC = 2.7V VREF = 2.5V 25
Reference Current vs Reference Voltage
fS = 150kHz TA = 25C VCC = 3.6V
20
20
15
15
10
10
5
5
0 -50 -25
0 50 25 75 0 TEMPERATURE (C) 100 125 0 0.5 1.0 1.5 2.0 2.5 3.0 REFERENCE VOLTAGE (V) 3.5 4.0
1860L/61L G05
1860L/61L G06
Typical DNL Curve
1.0 fS = 150kHz TA = 25C VCC = 2.7V VREF = 2.5V 100
Analog Input Leakage vs Temperature
CONV = 0V VCC = 2.7V VREF = 2.5V
0.5
75
0
50
-0.5
25
-1.0
0
512 1024 1536 2048 2560 3072 3584 4096 CODE
1860L/61L G08
0 -50 -25
50 25 75 0 TEMPERATURE (C)
100
125
1860L/61L G09
Change in Offset vs Temperature
1.0 0.8 fS = 150kHz VCC = 2.7V VREF = 2.5V 2
Change in Gain Error vs Reference Voltage
fS = 150kHz TA = 25C VCC = 3.6V 1
0
-1
-1.0 4
-50 -25
50 25 75 0 TEMPERATURE (C)
100
125
-2
0
2 3 1 REFERENCE VOLTAGE (V)
4
1860L/61L G12
1860L/61L G11
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LTC1860L/LTC1861L TYPICAL PERFOR A CE CHARACTERISTICS
Change in Gain Error vs Temperature
1.0 0.8 CHANGE IN GAIN ERROR (LSB) 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -50 -25 50 25 75 0 TEMPERATURE (C) 100 125 fS = 150kHz VCC = 2.7V VREF = 2.5V AMPLITUDE (dB) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 fIN (kHz)
1860L/61L G14
SNR (dB)
Signal-to-(Noise + Distortion) vs fIN
80 70 60 SINAD (dB) 50 THD (dB) 40 30 20 10 0 1 10 fIN (kHz) fS = 150kHz TA = 25C VCC = 3V VIN = 0dB VREF = 3V 100
1860L/61L G16
SFDR (dB)
PI FU CTIO S
LTC1860L high after the A/D conversion is finished, the part powers down. A logic low on this input enables the SDO pin, allowing the data to be shifted out. SDO (Pin 6): Digital Data Output. The A/D conversion result is shifted out of this pin. SCK (Pin 7): Shift Clock Input. This clock synchronizes the serial data transfer. VCC (Pin 8): Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane.
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VREF (Pin 1): Reference Input. The reference input defines the span of the A/D converter and must be kept free of noise with respect to GND. IN +, IN- (Pins 2, 3): Analog Inputs. These inputs must be free of noise with respect to GND. GND (Pin 4): Analog Ground. GND should be tied directly to an analog ground plane. CONV (Pin 5): Convert Input. A logic high on this input starts the A/D conversion process. If the CONV input is left
6
UW
1860L/61L G13
4096 Point FFT Non Averaged
80 fIN = 1kHz fS = 150kHz TA = 25C VCC = 3V VREF = 3V 70 60 50 40 30 20 10
SNR vs fIN
fS = 150kHz TA = 25C VCC = 3V VIN = 0dB VREF = 3V 1 10 fIN (kHz) 100
1860L/61L G15
Total Harmonic Distortion vs fIN
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 1 10 fIN (kHz) 100
1860L/61L G17
Spurious Free Dynamic Range vs fIN
100 90 80 70 60 50 40 30 20 10 0 1 10 fIN (kHz) fS = 150kHz TA = 25C VCC = 3V VIN = 0dB VREF = 3V 100
1860L/61L G18
fS = 150kHz TA = 25C VCC = 3V VIN = 0dB VREF = 3V
U
U
U
LTC1860L/LTC1861L
PI FU CTIO S
LTC1861L (MSOP Package) CONV (Pin 1): Convert Input. A logic high on this input starts the A/D conversion process. If the CONV input is left high after the A/D conversion is finished, the part powers down. A logic low on this input enables the SDO pin, allowing the data to be shifted out. CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must be free of noise with respect to AGND. AGND (Pin 4): Analog Ground. AGND should be tied directly to an analog ground plane. DGND (Pin 5): Digital Ground. DGND should be tied directly to an analog ground plane. SDI (Pin 6): Digital Data Input. The A/D configuration word is shifted into this input. SDO (Pin 7): Digital Data Output. The A/D conversion result is shifted out of this output. SCK (Pin 8): Shift Clock Input. This clock synchronizes the serial data transfer. VCC (Pin 9): Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. VREF (Pin 10): Reference Input. The reference input defines the span of the A/D converter and must be kept free of noise with respect to AGND. LTC1861L (SO-8 Package) CONV (Pin 1): Convert Input. A logic high on this input starts the A/D conversion process. If the CONV input is left high after the A/D conversion is finished, the part powers down. A logic low on this input enables the SDO pin, allowing the data to be shifted out. CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must be free of noise with respect to GND. GND (Pin 4): Analog Ground. GND should be tied directly to an analog ground plane. SDI (Pin 5): Digital Data Input. The A/D configuration word is shifted into this input. SDO (Pin 6): Digital Data Output. The A/D conversion result is shifted out of this output. SCK (Pin 7): Shift Clock Input. This clock synchronizes the serial data transfer. VCC (Pin 8): Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. VREF is tied internally to this pin.
FUNCTIONAL BLOCK DIAGRA
CONVERT CLK
IN + (CH0) IN - (CH1)
GND
W
U
U
U
U
U
VCC
CONV (SDI) SCK
BIAS AND SHUTDOWN DATA IN
SERIAL PORT
SDO
12-BITS
+ -
12-BIT SAMPLING ADC
DATA OUT
PIN NAMES IN PARENTHESES REFER TO LTC1861L
1860L/61L BD
VREF
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LTC1860L/LTC1861L
TEST CIRCUITS
Load Circuit for tdDO, tr, tf, tdis and ten
TEST POINT
Voltage Waveforms for SDO Rise and Fall Times, tr, tf
VOH VOL tr tf
SDO
3k SDO 20pF tdis WAVEFORM 1
1860 TC01
VCC tdis WAVEFORM 2, ten
1860 TC04
Voltage Waveforms for ten Voltage Waveforms for tdis
CONV
VIH
SDO ten
1860 TC03
CONV
Voltage Waveforms for SDO Delay Times, tdDO and thDO
SCK VIL tdDO thDO VOH SDO VOL
1860 TC02
SDO WAVEFORM 1 (SEE NOTE 1) tdis SDO WAVEFORM 2 (SEE NOTE 2)
90%
10%
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL
1860 TC05
APPLICATIO S I FOR ATIO
LTC1860L OPERATION Operating Sequence
The LTC1860L conversion cycle begins with the rising edge of CONV. After a period equal to t CONV, the conversion is finished. If CONV is left high after this time, the LTC1860L goes into sleep mode drawing only leakage current. On the falling edge of CONV, the LTC1860L goes into sample mode and SDO is enabled. SCK synchronizes the data transfer with each bit being transmitted from SDO on the falling SCK edge. The receiving system should capture the data from SDO on the rising edge of SCK. After completing the data transfer, if further SCK clocks are applied with CONV low, SDO will output zeros indefinitely. See Figure 1.
8
U
Analog Inputs The LTC1860L has a unipolar differential analog input. The converter will measure the voltage between the "IN + " and "IN - " inputs. A zero code will occur when IN+ minus IN - equals zero. Full scale occurs when IN+ minus IN - equals VREF minus 1LSB. See Figure 2. Both the "IN+ " and "IN - " inputs are sampled at the same time, so common mode noise on the inputs is rejected by the ADC. If "IN - " is grounded and VREF is tied to VCC, a rail-to-rail input span will result on "IN+ " as shown in Figure 3. Reference Input The voltage on the reference input of the LTC1860L (and the LTC1861L MSOP package) defines the full-scale range of the A/D converter. These ADCs can operate with reference voltages from VCC to 1V.
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W
UU
LTC1860L/LTC1861L
APPLICATIO S I FOR ATIO
CONV tCONV
SCK
DON'T CARE
SDO Hi-Z
Figure 1. LTC1860L Operating Sequence
1F
111111111111 111111111110
* * *
000000000001 000000000000
0V 1LSB VREF VREF - 1LSB VREF - 2LSB
*VIN = IN + - IN -
Figure 2. LTC1860L Transfer Curve
LTC1861L OPERATION Operating Sequence The LTC1861L conversion cycle begins with the rising edge of CONV. After a period equal to t CONV, the conversion is finished. If CONV is left high after this time, the LTC1861L goes into sleep mode. The LTC1861L's 2-bit data word is clocked into the SDI input on the rising edge of SCK after CONV goes low. Additional inputs on the SDI pin are then ignored until the next CONV cycle. The shift clock (SCK) synchronizes the data transfer with each bit being transmitted on the falling SCK edge and captured on the rising SCK edge in both transmitting and receiving systems. The data is transmitted and received simultaneously (full duplex). After completing the data transfer, if further SCK clocks are applied with CONV low, SDO will output zeros indefinitely. See Figure 4. Analog Inputs The two bits of the input word (SDI) assign the MUX configuration for the next requested conversion. For a
U
SLEEP MODE 1 2 3 4 5 t SMPL 6 7 8 9 10 11 12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0* Hi-Z *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY 1860 F01
VCC LTC1860L 1 VREF IN + IN - GND VCC SCK SDO CONV 8 7 6 5
1860 F03
W
UU
VIN*
VIN = 0V TO VCC
2 3 4
SERIAL DATA LINK TO ASIC, PLD, MPU, DSP OR SHIFT REGISTERS
1860 F02
Figure 3. LTC1860L with Rail-to-Rail Input Span
given channel selection, the converter will measure the voltage between the two channels indicated by the "+" and "-" signs in the selected row of Table 1. In single-ended mode, all input channels are measured with respect to GND (or AGND). A zero code will occur when the "+" input minus the "-" input equals zero. Full scale occurs when the "+" input minus the "-" input equals VREF minus 1LSB. See Figure 5. Both the "+" and "-" inputs are sampled at the same time so common mode noise is rejected. The input span in the SO-8 package is fixed at VREF = VCC. If the "-" input in differential mode is grounded, a rail-to-rail input span will result on the "+" input. Reference Input The reference input of the LTC1861L SO-8 package is internally tied to VCC. The span of the A/D converter is therefore equal to VCC. The voltage on the reference input of the LTC1861L MSOP package defines the span of the A/D converter. The LTC1861L MSOP package can operate with reference voltages from 1V to VCC.
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LTC1860L/LTC1861L
APPLICATIO S I FOR ATIO
CONV tCONV
SDI
DON'T CARE
SCK
DON'T CARE
SDO
Hi-Z
Figure 4. LTC1861L Operating Sequence
111111111111 111111111110
* * *
000000000001 000000000000 0V 1LSB VCC VCC - 1LSB VCC - 2LSB VIN*
*VIN = (SELECTED "+" CHANNEL) - (SELECTED "-" CHANNEL) REFER TO TABLE 1
Figure 5. LTC1861L Transfer Curve
GENERAL ANALOG CONSIDERATIONS Grounding The LTC1860L/LTC1861L should be used with an analog ground plane and single point grounding techniques. Do not use wire wrapping techniques to breadboard and evaluate the device. To achieve the optimum performance, use a printed circuit board. The ground pins (AGND and DGND for the LTC1861L MSOP package and GND for the LTC1860L and LTC1861L SO-8 package) should be tied directly to the analog ground plane with minimum lead length. Bypassing For good performance, the VCC and VREF pins must be free of noise and ripple. Any changes in the VCC/VREF voltage with respect to ground during the conversion cycle can
10
U
SLEEP MODE t SMPL S/D O/S 1 2 3 4 5 DON'T CARE 6 7 8 9 10 11 12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0* Hi-Z *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY
1860 F04
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UU
Table 1. Multiplexer Channel Selection
MUX ADDRESS SGL/DIFF ODD/SIGN 0 1 1 1 0 0 1 0 CHANNEL # 0 1 + + + - - + GND - -
SINGLE-ENDED MUX MODE DIFFERENTIAL MUX MODE
1860 F05
186465 TBL1
induce errors or noise in the output code. Bypass the VCC and VREF pins directly to the analog ground plane with a minimum of 1F tantalum. Keep the bypass capacitor leads as short as possible. Analog Inputs Because of the capacitive redistribution A/D conversion techniques used, the analog inputs of the LTC1860L/ LTC1861L have capacitive switching input current spikes. These current spikes settle quickly and do not cause a problem if source resistances are less than 200 or high speed op amps are used (e.g., the LT(R)1211, LT1469, LT1807, LT1810, LT1630, LT1226 or LT1215). But if large source resistances are used, or if slow settling op amps drive the inputs, take care to ensure the transients caused by the current spikes settle completely before the conversion begins.
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LTC1860L/LTC1861L
PACKAGE DESCRIPTIO
5.23 (.206) MIN
0.42 0.04 (.0165 .0015) TYP
RECOMMENDED SOLDER PAD LAYOUT 0.18 (.077) NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.889 0.127 (.035 .005)
5.23 (.206) MIN
3.2 - 3.45 (.126 - .136)
0.50 0.305 0.038 (.0197) (.0120 .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT 0.18 (.007) NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
.045 .005 .050 BSC .010 - .020 x 45 (0.254 - 0.508) .008 - .010 (0.203 - 0.254) .160 .005 .016 - .050 (0.406 - 1.270) NOTE: 1. DIMENSIONS IN .014 - .019 (0.355 - 0.483) TYP .050 (1.270) BSC .228 - .244 (5.791 - 6.197) 0- 8 TYP .053 - .069 (1.346 - 1.752) 8 .004 - .010 (0.101 - 0.254)
.245 MIN
.030 .005 TYP RECOMMENDED SOLDER PAD LAYOUT
INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
MS8 Package 8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
0.889 0.127 (.035 .005) 3.00 0.102 (.118 .004) (NOTE 3) 8 7 65 0.52 (.206) REF 3.2 - 3.45 (.126 - .136) GAUGE PLANE 0.65 (.0256) BSC DETAIL "A" 0.53 0.015 (.021 .006) 1 1.10 (.043) MAX 23 4 0.86 (.034) REF 0.254 (.010) DETAIL "A" 0 - 6 TYP 4.90 0.15 (1.93 .006) 3.00 0.102 (.118 .004) NOTE 4 SEATING PLANE 0.22 - 0.38 (.009 - .015) TYP 0.65 (.0256) BSC 0.13 0.076 (.005 .003)
MSOP (MS8) 0802
MS Package 10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
3.00 0.102 (.118 .004) (NOTE 3) 10 9 8 7 6 0.497 0.076 (.0196 .003) REF
0.254 (.010) GAUGE PLANE
DETAIL "A" 0 - 6 TYP
4.90 0.15 (1.93 .006)
3.00 0.102 (.118 .004) NOTE 4
12345 0.53 0.01 (.021 .006) DETAIL "A" 1.10 (.043) MAX 0.86 (.034) REF
SEATING PLANE
0.17 - 0.27 (.007 - .011) TYP
0.50 (.0197) BSC
0.13 0.076 (.005 .003)
MSOP (MS) 0802
S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.189 - .197 (4.801 - 5.004) NOTE 3 7 6 5
.150 - .157 (3.810 - 3.988) NOTE 3
1
2
3
4
SO8 0303
18601Lf
11
LTC1860L/LTC1861L
TYPICAL APPLICATIO
AGND 1F GAIN CONTROL
RELATED PARTS
PART NUMBER 12-Bit Serial I/O ADCs LTC1286/LTC1298 LTC1400 LTC1401 LTC1402 LTC1404 LTC1860/LTC1861 14-Bit Serial I/O ADCs LTC1417 LTC1418 16-Bit Serial I/O ADCs LTC1609 LTC1864/LTC1865 LTC1864L/LTC1865L References LT1460 LT1790 Micropower Precision Series Reference Micropower Low Dropout Reference Bandgap, 130A Supply Current, 10ppm/C, Available in SOT-23 60A Supply Current, 10ppm/C, SOT-23 200ksps 250ksps 150ksps 65mW 4.25mW 1.22mW Configurable Bipolar or Unipolar Input Ranges, 5V SO-8, MS8, 1-Channel, 5V/SO-8, MS, 2-Channel, 5V SO-8, MS8, 1-Channel, 3V/SO-8, MS, 2-Channel, 3V 400ksps 200ksps 20mW 15mW 16-Pin SSOP, Unipolar or Bipolar, Reference, 5V Serial/Parallel I/O, Internal Reference, 5V 12.5ksps/11.1ksps 400ksps 200ksps 2.2Msps 600ksps 250ksps 1.3mW/1.7mW 75mW 15mW 90mW 25mW 4.25mW 1-Channel with Ref. Input (LTC1286), 2-Channel (LTC1298), 5V 1-Channel, Bipolar or Unipolar Operation, Internal Reference, 5V SO-8 with Internal Reference, 3V Serial I/O, Bipolar or Unipolar, Internal Reference SO-8 with Internal Reference, Bipolar or Unipolar, 5V SO-8, MS8, 1-Channel, 5V/SO-8, MS, 2-Channel, 5V SAMPLE RATE POWER DISSIPATION DESCRIPTION
12
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
q
U
Tiny 2-Chip Data-Acquistion System
1F 3V 0.1F 8 3V
+
VIN 3 LTC6910-1
4 5
VREF 1 499 270pF
VCC
-
2
7
6
IN+ SCK LTC1860L IN - SDO GND CONV
ADC CONTROL
LTC6910-1 (IN TSOT-23 PACKAGE) COMPACTLY ADDS 40dB OF INPUT GAIN RANGE TO THE LTC1860L (IN MSOP 8-PIN PACKAGE). SINGLE 3V SUPPLY
1860L/61L TA03
18601Lf LT/TP 0303 2K * PRINTED IN USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2001

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